A low dropout voltage regulator (LDO) is a widely used circuit in electronic systems. The purpose of the LDO is to generate a constant output voltage as supply for other circuits in the electronic system and to isolate these circuits from each other to reduce cross talk via an external supply voltage. The dropout voltage can be defined as the minimum voltage over the regulator to substantially maintain its output voltage.
LDOs may be integrated on a semiconductor substrate in a so-called system-on-chip to save costs and to improve performance.
FIG. 1 shows a schematic layout of an LDO which is capable of providing a constant voltage supply for an electronic circuit. The electronic circuit is schematically depicted by a resistor Zload.
The LDO depicted in FIG. 1 has an output transistor T1, controlled by a feedback loop with an operational amplifier OA.
In this example an nMOS transistor T1 is connected with a drain terminal D to an external voltage supply Vsup. A gate terminal G of transistor T1 is connected to an output O1 of the opamp OA. A source terminal S of transistor T1 has a connection to a first negative input IN1 of the opamp OA.
External voltage supply Vsup is also connected to a power supply terminal IN3 of the opamp OA.
The source terminal S is further connected to a supply terminal X1 of the electronic circuit Zload. A second terminal X2 of Zload is connected to a ground potential line Vgnd. Parallel to the circuit Zload a capacitor Cload is connected between the source terminal S and ground potential Vgnd.
Further, a reference voltage signal Vref is provided to a second input of the opamp OA by a reference voltage source VS, which has one terminal connected to the second positive input IN2 of the opamp OA and the other terminal connected to ground potential Vgnd.
Adversely, the output voltage of the opamp OA at terminal O1 is a gate-source voltage above the output voltage Vout as measured on the source side S of the nMOS transistor T1. Assuming that the output O1 is limited by the supply voltage IN3, this implies that the LDO of FIG. 1 can not have a low dropout voltage, which poses a disadvantage in battery-powered circuits.
Many variations on the basic LDO of FIG. 1 exist.
For example, in one further type of LDO instead of an nMOS output transistor T1, a pMOS transistor is used as output transistor. In such an LDO, the output impedance will increase with frequency due to the roll-off of the control loop. A large external capacitor Cload (compared to the capacitor required in an LDO based on an nMOS transistor) is needed to maintain a low output impedance for high frequencies. The need for this large capacitor is a major drawback of this kind of LDO. Each LDO requires a dedicated pin for the capacitor. This adds significantly to costs especially in situations where many circuits each comprise a pMOS transistor based LDO.
In another type of nMOS transistor based LDO as described in e.g., G. den Besten, B. Nauta, “Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC's in 3.3V CMOS Technology,” IEEE J. Solid-State Circuits, vol. 33, July 1998, pp. 956-962, the opamp OA is replaced by a charge pump circuit. The charge pump circuit is capable of driving the gate of the output transistor to a voltage above the supply voltage Vsup. Thus, such an LDO can have a low dropout voltage. Disadvantageously, this type of LDO provides an output voltage which is not constant due to electronic properties of the charge pump: the charge pump can generally not react as fast as an opamp OA, so a sudden change in external supply or in load impedance will result in a larger distortion than would occur in the case of the standard nMOS transistor based LDO voltage regulator. Moreover, the charge-pump uses a clock to generate the high voltage: the output voltage of the charge pump shows small voltage steps instead of having a constant level. The output voltage Vout of the LDO will follow these steps, i.e., shows a ripple, and will not be constant.
Another type of LDO as disclosed in U.S. Pat. No. 5,162,668 is based on an nMOS transistor with an opamp OA combined with a charge pump. Again, due to the properties of the charge pump, the output voltage Vout of such an LDO may still show a ripple, which hinders application in sensitive analog circuits.
The prior art also discloses cascading of different types of LDOs. An example of a cascaded voltage regulator has been described in V. Gupta, G. Rincon-Mora, “A Low Dropout, CMOS Regulator with High PSR over Wideband Frequencies,” in Proc. ISCAS2005, 2005, pp. 4245-4248, which shows a pMOS based LDO in cascade with a charge-pump driven nMOS based LDO. In this type of LDO circuit the series connection of the pMOS and nMOS transistor does however adversely increase the dropout voltage. In addition, the cascade causes a generation of a cross-talk signal from the charge pump to the pMOS transistor that may interfere with the output voltage Vout.
Due to the possibility for integration on-chip in semiconductor devices, LDOs are potentially well suited for digital wireless communication applications. In many systems based on digital wireless communication (for instance GSM, DECT, Bluetooth, IEEE 802.11), communication only takes place in certain time-slots within a time frame. For the reason of power-saving, a receiver is designed to be powered-down as much of the time as possible. This means that during each time frame, there will be one or more periods that receiver-related circuits are in power-down mode and a constant supply voltage is not needed.
It is an object of the present invention to provide a low dropout voltage regulator which is capable of delivering a substantially constant output voltage especially in time-slot based operation devices.